I. Field of the Invention
The present invention relates to computer systems, and more particularly, to a computer architecture for providing high performance addressing of and data transfers to processors in a multiprocessor (MP) system.
II. Related Art
As a consequence of the rapidly evolving personal computer (PC) industry, high end PCs have migrated into high performance applications which were traditionally handled by minicomputers or mainframe computers. These high performance applications require interaction with many peripherals at high speeds as well as manipulation of enormous amounts of data to provide real time operation as perceived by the PC user.
As a result, multiple processors have been implemented in PC architectures to maximize speed by allocation of tasks and responsibilities which can be performed in parallel. By design, the independent processors of a multiprocessor (MP) system usually execute instructions simultaneously via a multithread instruction set to concurrently process transactions.
As more and more processors are added to an MP system, the communication and control of processors becomes more complex. Generally, the processors must communicate via a bus network comprised of several buses. Moreover, the addressing of processors and the transmission of data to processors via the bus network pose an extreme burden on an MP system as more processors are added. One reason is that an increase in traffic on the bus network occurs with an increase in the number of processors because more processors fight for control of the buses in order to perform addressing and data transfer functions. Thus, the MP system becomes slower and the total number of processors which may be implemented is limited.
Furthermore, as more processors are added to the MP system, processor time delays increase while processors fight for control of the buses and must wait until receiving control. Consequently, the purpose of adding processors to increase speed by concurrent processing of data is defeated because of the increase in processor delays, which equates to wasted processor time.
Finally, because many different types of buses and processors for PC architectures exist in the industry, any solution to the foregoing problems should be flexible in implementation. A solution should accommodate the protocols and compatibility models of the various types of commercially available buses and processors which may be incorporated into the MP system to be cost justified.